Whole chip ESD protection

ABSTRACT

This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to a whole chip electrostatic discharge,ECD, circuit and method.

[0003] In particular, this invention relates to distributing the circuitof this invention next to each input/output pad in order to provideparallel ESD current discharge paths.

[0004] 2. Description of Related Art

[0005]FIG. 1 shows a prior art input/output protection circuit. Thisprotection circuit is placed next to each input/output (I/O) pad. Eachprotection circuit, like the one shown in FIG. 1, is used to protectonly one I/O pad. If one of the I/o pads is zapped with high voltage orhigh current, the electrostatic discharge, ESD, current 170 only flowsthrough the protection circuit adjacent to the zapped I/o pad. Thecircuit in FIG. 1 is connected to the supply voltage Vcc 190 and to Vss150 or ground. The circuit includes a p-channel metal oxidesemiconductor field effect transistor PMOS FET device 110 and ann-channel metal oxide semiconductor field effect transistor NMOS FETdevice 120. It also includes a bipolar junction transistor 180 and aresistor 160.

[0006] U.S. Pat. No. 6,344,412 (Ichikawa, et al.) “An Integrated ESDprotection method and system” describes a method and a system forprotecting integrated circuits from electrostatic discharge damage.

[0007] U.S. Pat. No. 6,262,873 (Pequignot, et al.) “A Method forProviding ESD Protection for an Integrated Circuit” discloses a methodfor providing electrostatic protection for integrated circuits.

[0008] U.S. Pat. No. 6,218,704 (Brown, et al.) “ESD Protection Structureand Method” discloses an integrated circuit structure and method forelectrostatic discharge protection for chips.

BRIEF SUMMARY OF THE INVENTION

[0009] It is the objective of this invention to provide a whole chipelectrostatic discharge, ECD, circuit and method.

[0010] It is further an object of this invention to provide a means ofdistributing the circuit of this invention next to each input/output padin order to provide parallel ESD current discharge paths.

[0011] The objects of this invention are achieved by a whole chipelectrostatic discharge, ECD, first embodiment circuit made up of a PNdiode whose p-side connects to the input/output, I/O pad to be protectedand whose N-side is connected to Vcc supply voltage, a PMOS FET plusNMOS FET 2-device input stage connected between Vcc and Vss, a resistorplus NMOS FET first mid stage connected between Vcc and Vss (ground).The circuit of the invention also contains a resistor to ground secondmid-stage, and a PMOS FET plus NMOS FET output stage connected betweenVcc and Vss (ground) whose input connects from the mid stages and whoseoutput drives an unused I/O pad.

[0012] The objects of this invention are further achieved by a wholechip electrostatic discharge ECD method comprising the steps ofconnecting all input/output, I/O pads to each other with doubleisolation, and inserting a circuit of the first embodiment of thisinvention between each adjacent I/O pair on a semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 shows a prior art input/output protection circuit.

[0014]FIG. 2 shows a block diagram of an integrated circuit with theinput/output pins.

[0015]FIG. 3 shows parallel circuit example of this invention.

[0016]FIG. 4 shows circuit embodiment #1 of this invention.

[0017]FIG. 5 shows circuit embodiment #2 of this invention.

DETAILED DESCRIPTION OF THE INVENTION

[0018]FIG. 2 shows block diagram which represents an integrated circuit240 with several input/output (I/O) pins 200, 210. Pin 200 is the pinunder test or the zapped pin with either a high voltage or high current.The non-zapped I/O pin 210 is also shown. In this invention, all of thepins or I/o pads have the protection circuit of this invention adjacentto them. When one of the I/O pads is zapped such as pin 200 in FIG. 2,all of the protection circuit associated with all of the I/O pads 200,200 including the zapped and unzapped I/O pads participate in a parallelcircuit combination which greatly improves the whole chip ESDprotection.

[0019]FIG. 3 shows an example of the composite parallel circuit whichresults when an I/O pad is zapped. The zapped I/O pad is shown 390.Devices 380 and 370 are from the ESD protection circuit adjacent to thezapped I/o pad 390. Devices 340 and 350 are from an unzapped I/O pad.Similarly devices 345 and 355 are from another unzapped I/O pad. Node395 is the common discharge mode shared by the parallel connection ofthese I/O protection circuits. Node 315 is the shared Vcc power supplynode for all of the I/O protection circuits. Node 325 is the sharedground node for all of the I/O protection circuits.

[0020] Blocks 330 represents pre-drive for the first PMOS FET device 345in the parallel protection circuit of FIG. 3. Similarly, block 340represents a pre-driver for the first NMOS FET device 355 in theparallel protection circuit of FIG. 3. Also shown in FIG. 3 are thepre-drive P control signal 310 and the pre-drive N control signal 320.

[0021]FIG. 4 shows the first embodiment circuit of this invention. Thezapped I/O pad 410 is the pad, which has an abnormally high voltage orcurrent. The first embodiment circuit of this invention is made up ofPMOS FET device 430 whose drain is connected to the zapped I/O 410.There are actually several PMOS FETs like 430 connected in parallel. Thesource of the PMOS FET device 430 is connected to the Vcc power supply.The gate of the PMOS FET device 430 is connected with the Vpg common ‘p’node, which is shared by all of the parallel connected protectioncircuits of this invention. Device 430 is normally off during normaloperations when there is no ESD high voltage or high current situation.

[0022]FIG. 4 also shows NMOS FET device 440 whose source is connected toVss or ground 475 and whose drain is connected to the zapped I/O pad410. There are actually several NMOS FETs like 440 connected inparallel. The gate of the NMOS FET device 440 is connected to the Vngcommon ‘N’ node, which is shared by all of the parallel connectedprotection circuits of this invention. Device 440 is normally off duringnormal operations when there is no ESD high voltage or high currentsituation.

[0023]FIG. 4 also shows a PN diode 420 whose p-side is connected to thezapped I/O pad 410 & whose N side is connected to the Vcc power supply485. The PN diode 420 conducts only when the voltage at the I/O pad 410exceeds Vcc and Vbe where Vbe is a diode voltage drop of about 0.7volts. The voltage at a zapped I/O pin 410 is clamped to Vcc and Vbe.During this high voltage clamped state NMOS FET device 440 is ‘ON’ andconducting ESD current to ground. Node 465 is high due to AC currentthrough the 1 kilohm resistor 470, coupling from node 410 to node 465via Cds 441 and NMOS device 440. Node 465 goes high and stays high for atime period since the parasitic capacitance Cgs 471 of NMOS FET device480 charges up. This charged up high voltage turns on NMOS device 460which provides another parallel path for ESD current to flow to groundvia the 1 kilohm resistor 450. This current flow-through the turned onNMOS FET 460 to ground 475 produces a low level at the Vpg node. The lowlevel at node Vpg 431 turns on PMOS FET 490. In addition, the previouslymentioned current flow through the 1 kilo ohm resistor 470 causes a highvoltage level at the Vng node 465. This high level at Vng 465 turns onthe NMOS FET 480. Therefore a third parallel ESD current discharge pathto ground is established through devices 490 and 480. Nodes Vpg and Vngare nodes which are shared by all of the parallel ESD protectioncircuits like the one in FIG. 4. All of the ESD protection circuitsassociated with the unzapped I/O pads provide several parallel paths toground for the ESD current to discharge. This quick discharging of theESD current to ground protects the whole chip from ESD overcurrentdamage.

[0024] In summary, a positive ESD voltage spike causes the capacitivecharging of Vng to turn on both PMOS 430 and NMOS 440 devices in thezapped and unzapped protection circuits. A negative ESD voltage spike isclamped by the PN diode 420 at the zapped I/O pin. The PMOS 430 and NMOS440 devices are off and the unzapped protection circuits are off.

[0025]FIG. 5 shows the first embodiment circuit of this invention. Thezapped I/O pad 510 is the pad, which has an abnormally high voltage orcurrent. The first embodiment circuit of this invention is made up ofPMOS FET device 530 whose drain is connected to the zapped I/O 510. Thesource of the PMOS FET device 530 is connected to the Vcc power supply.The gate of the PMOS FET device 530 is connected with the Vpg common ‘p’node, which is shared by all of the parallel connected protectioncircuits of this invention. Device 530 is normally off during normaloperations when there is no ESD high voltage or high current situation.

[0026]FIG. 5 also shows NMOS FET device 540 whose source is connected toVss or ground 575 and whose drain is connected to the zapped I/O pad510. The gate of the NMOS FET device 540 is connected to the Vng common‘N’ node, which is shared by all of the parallel connected protectioncircuits of this invention. Device 540 is normally off during normaloperations when there is no ESD high voltage or high current situation.

[0027]FIG. 5 also shows a PN diode 520 whose p-side is connected to thezapped I/O pad 510 & whose N side is connected to the Vcc power supply585. The PN diode 520 conducts only when the voltage at the I/O pad 510exceeds Vcc and Vbe where Vbe is a diode voltage drop of about 0.7volts. The voltage at a zapped I/O pin 510 is clamped to Vcc and Vbe.During this high voltage clamped state NMOS FET device 540 is ‘ON’ andconducting ESD current to ground. Node 565 is high due to AC currentthrough the active resistor made up of the NMOS FET device 570, couplingfrom node 510 to node 565 via Cds 541 and NMOS device 540. Since nodeVpg 531 goes low, NMOS device 570 will eventually turn off. This furtherenhances the high level at node Vng 565. Node 565 goes high and stayshigh for a time period since the parasitic capacitance Cgs 571 of NMOSFET device 580 charges up. This charged up high voltage turns on NMOSdevice 560 which provides another parallel path for ESD current to flowto ground via the 1 kilohm resistor 550. This current flow through theturned on NMOS FET 560 to ground 575 produces a low level at the Vpgnode. The low level at node Vpg 531 turns on PMOS FET 590. In addition,the previously mentioned current flow through the 1 kilo ohm resistor570 causes a high voltage level at the Vng node 565. This high level atVng 565 turns on the NMOS FET 580. Therefore a third parallel ESDcurrent discharge path to ground is established through devices 590 and580. Nodes Vpg and Vng are nodes which are shared by all of the parallelESD protection circuits like the one in FIG. 5. All of the ESDprotection circuits associated with the unzapped I/O pads provideseveral parallel paths to ground for the ESD current to discharge. Thisquick discharging of the ESD current to ground protects the whole chipfrom ESD overcurrent damage.

[0028] In summary, a positive ESD voltage spike causes the capacitivecharging of Vng to turn on both PMOS 530 and NMOS 540 devices in thezapped and unzapped protection circuits. A negative ESD voltage spike isclamped by the PN diode 520 at the zapped I/O pin. The PMOS 530 and NMOS540 devices are off and the unzapped protection circuits are off.

[0029] The advantage of this invention is the ability to create aparallel discharge path to ground in order to discharge the damaging ESDcurrent quickly so as to avoid circuit damage. The two circuitembodiments show how the protection circuits of this invention at boththe unzapped I/O pads and the zapped I/O pad are connected in a parallelcircuit for discharging ESD currents quickly. These protectionembodiments require a small amount of semiconductor area, since thesmaller protection circuits are distributed and placed at the locationsof each I/O pad.

[0030] While this invention has been particularly shown and describedwith Reference to the preferred embodiments thereof, it will beunderstood by those Skilled in the art that various changes in form anddetails may be made without Departing from the spirit and scope of thisinvention.

What is claimed is:
 1. A whole chip electrostatic discharge, ECD, firstembodiment circuit comprising: a PN diode whose p-side connects to theinput/output, I/O pad to be protected and whose N-side is connected toVcc supply voltage, a PMOS FET plus NMOS FET 2-device input stageconnected between Vcc and Vss, a resistor plus NMOS FET first mid stageconnected between Vcc and Vss (ground), a resistor to ground secondmid-stage, and a PMOS FET plus NMOS FET output stage connected betweenVcc and Vss (ground) whose input connects from the mid stages and whoseoutput drives an unused I/O pad.
 2. The whole chip ESD protectioncircuit of claim 1 wherein said input stage contains said PN diode whoseP-side is connected to the I/O pad to be protected and whose N-side isconnected to Vcc.
 3. The whole chip ESD protection circuit of claim 1wherein said input stage contains said p-channel metal oxidesemiconductor field effect transistor PMOS FET whose source is connectedto Vcc and is common to the N-side of said PN diode, whose drain isconnected in common with the p-side of said PN diode, and to the drainof said NMOS FET in the input stage, and whose gate is connected to saidmid stage circuit.
 4. The whole chip ESD protection circuit of claim 1wherein said input stage contains said n-channel metal oxidesemiconductor field-effect transistor NMOS FET whose source is connectedto Vss or ground, whose drain is connected in common with said p-side ofsaid PN diode and in common with said I/O pad to be protected and incommon with said drain of said PMOS FET in said input stage, and whosegate is connected to said mid stage circuit.
 5. The whole chip ESDprotection circuit of claim 1 wherein said first mid-stage contains anNMOS FET whose source is connected to ground, whose drain is connectedto said gate of said PMOS FET of said input stage and is connected tosaid resistor of this 1^(st) mid stage and is connected to said outputstage.
 6. The whole chip ESD protection circuit of claim 1 wherein saidfirst mid-stage contains a resistor connected between said VCC powersupply and said drain of said NMOS FET.
 7. The whole chip ESD protectioncircuit of claim 1 wherein said second mid-stage contains a resistorconnected between Vss or ground and between the gate of said NMOS FET insaid first mid-stage, the gate of said NMOS FET of said first stage, andwhich is connected to the input of said output stage.
 8. The whole chipESD protection circuit of claim 1 wherein said output stage containssaid PMOS FET whose source is connected to Vcc, whose drain is connectedto an unzapped I/O pad, and to the drain of said NMOS FET in the outputstage, and whose gate is connected to said gate of said PMOS FET in saidinput stage and connected to said drain of said NMOS FET in said inputstage.
 9. The whole chip ESD protection circuit of claim 1 wherein saidoutput stage contains said NMOSFET whose source is connected to Vss orground, whose drain is connected to an unzapped I/O pad and connected tosaid drain of said PMOS FET in said output stage and whose gate isconnected to said NMOS FET of said input stage and to one side of saidresistor in said 2^(nd) mid-stage and connected to said gate of saidNMOS FET of said first mid-stage.
 10. The whole chip ESD protectioncircuit of claim 1 wherein several said first embodiment circuits (onefor each I/O pad) are tied in parallel between Vcc and ground, in orderto sink large ESD charge and current.
 11. The whole chip ESD protectioncircuit of claim 1 wherein a drain to source intrinsic capacitor, Cds,of said NMOS FET in said input stage is used to couple charge from saidzapped I/O pad to said input to said output stage.
 12. The whole chipESD protection circuit of claim 1 wherein said charge coupled throughsaid intrinsic capacitance, Cds, of said NMOS FET of said input stagecharges up an intrinsic capacitance, Cgs, of said NMOS FET of saidoutput stage.
 13. A whole chip electrostatic discharge, ECD, secondembodiment circuit comprising: a PN diode whose p-side connects to theinput/output, I/O pad to be protected and whose N-side is connected toVcc supply voltage, a PMOS FET plus NMOS FET 2-device input stageconnected between Vcc and Vss, a resistor plus NMOS FET first mid stageconnected between Vcc and Vss (ground), a second mid-stage containing asecond NMOS FET connected between input stage and ground, and a PMOS FETplus NMOS FET output stage connected between Vcc and Vss (ground) whoseinput connects from the mid stages and whose output drives an unused I/Opad.
 14. The whole chip ESD protection circuit of claim 13 wherein saidinput stage contains said PN diode whose P-side is connected to the I/Opad to be protected and whose N-side is connected to Vcc.
 15. The wholechip ESD protection circuit of claim 13 wherein said input stagecontains said p-channel metal oxide semiconductor field effecttransistor PMOS FET whose source is connected to Vcc and is common tothe N-side of said PN diode, whose drain is connected in common with theaside of said PN diode, and to the drain of said NMOS FET in the inputstage, and whose gate is connected to said mid stage circuit.
 16. Thewhole chip ESD protection circuit of claim 13 wherein said input stagecontains said n-channel metal oxide semiconductor field effecttransistor NMOS FET whose source is connected to Vss or ground, whosedrain is connected in common with said p-side of said PN diode and incommon with said I/O pad to be protected and in common with said drainof said PMOS FET in said input stage, and whose gate is connected tosaid mid stage circuit.
 17. The whole chip ESD protection circuit ofclaim 13 wherein said first mid-stage contains an NMOS FET whose sourceis connected to ground, whose drain is connected to said gate of saidPMOS FET of said input stage and is connected to said resistor of this1^(st) mid stage and is connected to said output stage.
 18. The wholechip ESD protection circuit of claim 13 wherein said first mid-stagecontains a resistor connected between said VCC power supply and saiddrain of said NMOS FET.
 19. The whole chip ESD protection circuit ofclaim 13 wherein said second mid-stage contains an NMOS FET whose drainis connected to said gate of said NMOS FET in said first mid-stage,whose source is connected to Vss or ground, and whose gate is connectedto said gate of said PMOS FET of said first stage.
 20. The whole chipESD protection circuit of claim 13 wherein said output stage containssaid PMOS FET whose source is connected to Vcc, whose drain is connectedto an unzapped I/O pad, and to the drain of said NMOS FET in the outputstage, and whose gate is connected to said gate of said PMOS FET in saidinput stage and connected to said drain of said NMOS FET in said inputstage.
 21. The whole chip ESD protection circuit of claim 13 whereinsaid output stage contains said NMOSFET whose source is connected to Vssor ground, whose drain is connected to an unzapped I/O pad and connectedto said drain of said PMOS FET in said output stage and whose gate isconnected to said NMOS FET of said input stage and to the drain of saidNMOS FET of said 2^(nd) mid-stage and connected to said gate of saidNMOS FET of said first mid-stage.
 22. The whole chip ESD protectioncircuit of claim 13 wherein several said first embodiment circuits (onefor each I/O pad) are tied in parallel between. Vcc and ground, in orderto sink large ESD charge and current.
 23. The whole chip ESD protectioncircuit of claim 13 wherein a drain to source intrinsic capacitor, Cds,of said NMOS FET in said input stage is used to couple charge from saidzapped I/O pad to said input to said output stage.
 24. The whole chipESD protection circuit of claim 13 wherein said charge coupled throughsaid intrinsic capacitance, Cds, of said NMOS FET of said input stagecharges up an intrinsic capacitance, Cgs, of said NMOS FET of saidoutput stage.
 25. A whole chip electrostatic discharge ECD methodcomprising the steps of: connecting all input/output, I/O pads to eachother with double isolation, and inserting a circuit of the firstembodiment of this invention between each adjacent I/O pair on asemiconductor chip.
 26. The whole chip ECD method of claim 25 furthercomprising the steps of: including a PN diode whose p-side connects tothe input/output, I/O pad to be protected and whose-N-side is connectedto Vcc supply voltage, including a PMOS FET plus NMOS FET 2-device inputstage connected between Vcc and Vss, including a resistor plus NMOS FETfirst mid stage connected between Vcc and Vss (ground), including aresistor to ground second mid-stage, and including a PMOS FET plus NMOSFET output stage connected between Vcc and Vss (ground) whose inputconnects from the mid stages and whose output drives an unused I/O pad.27. A whole chip electrostatic discharge ECD method comprising the stepsof: connecting all input/output, I/O pads to each other with doubleisolation, and inserting a circuit of the second embodiment of thisinvention between each adjacent I/O pair on a semiconductor chip. 28.The whole chip ECD method of claim 27 further comprising the steps of:including a PN diode whose p-side connects to the input/output, I/O padto be protected and whose N-side is connected to Vcc supply voltage,including a PMOS FET plus NMOS FET 2-device input stage connectedbetween Vcc and Vss, including a resistor plus NMOS FET first mid stageconnected between Vcc and Vss (ground), including an NMOS FET in asecond mid-stage connecting both the input stage and the output stage,and including a PMOS FET plus NMOS FET output stage connected betweenVcc and Vss (ground) whose input connects from the mid stages and whoseoutput drives an unused I/O pad.